1.1. Design Components
The DisplayPort Intel® FPGA IP core design example requires these components.
|Core System (Platform Designer)||
The core system consists of the Nios II processor and its necessary components, DisplayPort TX core sub-system and the Video and Image Processing (VIP) FPGA IPs.
This system provides the infrastructure to interconnect the Nios II processor with the DisplayPort Intel® FPGA IP core (TX instance) through Avalon Memory Mapped (Avalon-MM) interface within a single Platform Designer system to ease the software build flow.
This system consists of:
|TX Sub-System (Platform Designer)||
The TX sub-system consists of:
|TX PHY Top||
The TX PHY top level consists of the components related to the transmitter PHY layer.
Note: 8.1 Gbps is available only in the Intel® Quartus® Prime Pro Edition software.
IOPLL generates three common source clocks:
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