AN 883: Intel Arria 10 DisplayPort TX-only Design

ID 683597
Date 7/03/2021

1.1. Design Components

The DisplayPort Intel® FPGA IP core design example requires these components.
Table 1.  Core System Components
Module Description
Core System (Platform Designer)

The core system consists of the Nios II processor and its necessary components, DisplayPort TX core sub-system and the Video and Image Processing (VIP) FPGA IPs.

This system provides the infrastructure to interconnect the Nios II processor with the DisplayPort Intel® FPGA IP core (TX instance) through Avalon Memory Mapped (Avalon-MM) interface within a single Platform Designer system to ease the software build flow.

This system consists of:
  • CPU Sub-System
  • TX Sub-System
TX Sub-System (Platform Designer)
The TX sub-system consists of:
  • Clock Source—The clock source to the DisplayPort TX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
  • DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard version 1.4.
  • Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints out in the Nios II Debug terminal. This component is only used when the TX_AUX_DEBUG parameter is turned on.
  • PIO—The parallel IO that triggers the DPTX register update in software (tx_utils.c).
  • Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon-MM interface between components within the TX sub-system to the Nios II processor in the Core sub-system.
Table 2.  DisplayPort TX PHY Top Components
Module Description
The TX PHY top level consists of the components related to the transmitter PHY layer.
  • Transceiver Native PHY(TX)—The transceiver block that receives 20-bit or 40-bit parallel data from the DisplayPort Intel® FPGA IP core and serializes the data before transmitting it. This block supports up to 8.1 Gbps (HBR3) data rate with 4 channels.
    Note: You must set the TX channel bonding mode to PMA and PCS bonding and the PCS TX Channel bonding master parameter to 0 (default is auto).
  • Transceiver PHY Reset Controller—The TX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing.
  • TX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY and TX PLL blocks to transmit serial data in the required data rates (RBR, HBR, HBR2, and HBR3).
  • TX PLL—The transmitter PLL block provides a fast serial fast clock to the Transceiver Native PHY block. For the DisplayPort Intel® FPGA IP core design example, Intel® uses transmitter fractional PLL (FPLL).
Note: 8.1 Gbps is available only in the Intel® Quartus® Prime Pro Edition software.
Table 3.  Top-Level Common Blocks
Module Description

IOPLL generates three common source clocks:

  • 160 MHz—Used as main clock for Clocked Video Output II and Test Pattern Generator II FPGA IPs.
  • 16 MHz—Used as DisplayPort TX auxiliary clock.
  • 148.5 MHz—Used as video clock for DisplayPort Intel® FPGA source and Clocked Video Output II FPGA IP

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