AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.4.2. Compiling and Testing the Design

You can download the DisplayPort TX-only design file (A10_DP_TX_FMC_PRO.par) from the Intel Design Store. To compile and run a demonstration test on the hardware example design, follow these steps.
The .par file contains includes pre-compiled .sof and .elf files that you can run to test the design.
  1. To extract the files in the .par file, refer to the Installation Package instruction in the Intel Design Store design download page.
  2. Extract and unzip the Additional_Files.zip file from the A10_DP_TX_FMC_PRO.par file, and move the Script and Software folder to the main project directory.
  3. Launch the Intel® Quartus® Prime Pro Edition software and open <project directory>/quartus/top.qpf.
    Note:

    Bitec DisplayPort FMC daughter card revision 10 has schematic changes compared to revisions 8 and earlier. Revision 8 has lane reversal and polarity inversion at TX. To support all revisions, the design example top level RTL file at <project directory>/rtl/top.v file include a local parameter for you to select the FMC revision. 

    localparam BITEC_DP_CARD_REV = 0;
    // 0 = Bitec FMC DP card rev.4 - 8,
    // 1 = rev.9 or later
  4. Open Nios II Command Shell and navigate to the Script folder.
  5. Run the build_sw_sh script in the Nios II terminal to build the software.
  6. In the Intel® Quartus® Prime Pro Edition software, click Processing > Start Compilation.
  7. After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
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