AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design

Document Version Changes
2021.07.03
  • Edited the Description for TX Video Clock in Table: Clocking Scheme Signals.
  • Added the steps to extract the files in the .par file in Compiling and Testing the Design.
  • Added the software version 18.1 for Intel® Quartus® Prime Pro Edition in Creating the TX-only Design with Bitec FMC Daughter Card.
  • Added a note and renamed Table: Example of IP Parameters Value to Generate a 4kp60 Output Video.
  • Added subtopic Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File and Removing Irrelevant Block in Platform Designer in section Removing Irrelevant Blocks.
  • Edited the Instantiating Video and Image Processing (VIP) Intel FPGA IPs.
    • Changed the Value from 8 to 10 for Bits per pixel per color plane in Table: Clocked Video Output (CVO) II and Test Pattern Generator (TPG) IIParameter Settings.
    • Edited Figure: Connecting CVO II Intel FPGA IP to the DisplayPort TX Sub-system.
    • Added Figure: Video PLL with tx_vid_clk output.
  • Added a new column Signal Name in the Table: DisplayPort TX-only Design Generated Clocks.
  • Changed Figure: Bitec Reconfig and TX Transceiver Block Connection.
  • Added the instructions in Modifying the Software.
2019.02.20 Initial release.
Level Two Title