AN 883: Intel Arria 10 DisplayPort TX-only Design

ID 683597
Date 7/03/2021

1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design

Document Version Changes
  • Edited the Description for TX Video Clock in Table: Clocking Scheme Signals.
  • Added the steps to extract the files in the .par file in Compiling and Testing the Design.
  • Added the software version 18.1 for Intel® Quartus® Prime Pro Edition in Creating the TX-only Design with Bitec FMC Daughter Card.
  • Added a note and renamed Table: Example of IP Parameters Value to Generate a 4kp60 Output Video.
  • Added subtopic Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File and Removing Irrelevant Block in Platform Designer in section Removing Irrelevant Blocks.
  • Edited the Instantiating Video and Image Processing (VIP) Intel FPGA IPs.
    • Changed the Value from 8 to 10 for Bits per pixel per color plane in Table: Clocked Video Output (CVO) II and Test Pattern Generator (TPG) IIParameter Settings.
    • Edited Figure: Connecting CVO II Intel FPGA IP to the DisplayPort TX Sub-system.
    • Added Figure: Video PLL with tx_vid_clk output.
  • Added a new column Signal Name in the Table: DisplayPort TX-only Design Generated Clocks.
  • Changed Figure: Bitec Reconfig and TX Transceiver Block Connection.
  • Added the instructions in Modifying the Software.
2019.02.20 Initial release.