AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.5.2.2. Removing Irrelevant Block in Platform Designer

Below are detailed steps to remove the irrelevant blocks in Platform Designer
  1. From Quartus Project Navigator, double click to open dp_core system.
  2. Remove dp_rx sub-system.
  3. Remove i2c_master.
  4. Remove unused RX components - dp_rx_clk_16 bridge and dp_rx_reset_bridge.
    Note: Before generating HDL, save the changes in Platform Designer, Sync System Info and Validate System Integrity to ensure no errors were introduced.
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