1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs
After removing irrelevant blocks in the design, instantiate the relevant Video and Image Processing FPGA IPs.
- Instantiate the Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II Intel® FPGA IPs in the Platform Designer and specify the parameters. The table below is an example of parameter value that generates a 4kp60 video.
Note: The Test Pattern Generator (TPG) II Intel® FPGA IP generates video stream that displays color bars video pattern. The Clocked Video Output II Intel® FPGA IP converts the Avalon-ST video format received from the TPG II Intel® FPGA IP to standard clocked video format.Note: Certain sink devices may not be able to accept below video resolution and settings. Contact sink device manufacturer for more information.
Table 7. Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II Parameter Settings FPGA IP Parameters Value Clocked Video Output IINote: The CVO II parameter setting is specific for 4K video resolution. For other video resolution, refer to VESA monitor timing standard specifications. Image width / Active pixels 3840 Image height / Active lines 2160 Bits per pixel per color plane 10 Number of color planes 3 Number of pixels in parallel 4 Separate syncs only - Frame/ Field 1 Horizontal sync 32 Separate syncs only - Frame/ Field 1 Horizontal front porch 48 Separate syncs only - Frame/ Field 1 Horizontal back porch 80 Separate syncs only - Frame/ Field 1 Vertical sync 5 Separate syncs only - Frame/ Field 1 Vertical front porch 3 Separate syncs only - Frame/ Field 1 Vertical back porch 54 Pixel FIFO size 3840 FIFO level at which to start output 3839 Use control port 4 Test Pattern Generator II Bits per color sample 10 Number of pixels in parallel 4 Color planes transmitted in parallel Yes Output format 4:4:4 Maximum frame width 3840 Maximum frame height 2160 Default Interlacing Progressive output Number of test patterns 1 Pattern Color bars Subsampling & Colorspace RGB
- Add Clock Bridge (160MHz clock input to TPG II and CVO II) for VIP and export out the input port.
- Add Reset Bridge (active low reset with none synchronous edges) for VIP and export out the input port.
- Connect the CVO II and TPG II Intel® FPGA IP instances in the Platform Designer.
Figure 6. Connecting the CVO II and TPG II in the Platform DesignerNote: The CVO II and TPG II Intel® FPGA IPs share the reset input from the reset generator output. Ensure the Clocked Video Port of CVO II FPGA IP signals are exported out from Platform Designer.
- Save the changes, run Sync System Info & Validate System Integrity. After that, proceed to Generate HDL.
Note: By adding TPG II, CVO II, Clock and Reset Bridge in the system, design top level instantiations of dp_core modules needs to be updated. Refer to the Instantiation Template in Platform Designer and update your top level instantiation accordingly.Note: Ensure the TPG II, CVO II, Clock and Reset Bridge are listed in the Quartus Project Navigator. If it is not available, manually add the IPs in the Quartus Settings > Files.
- At the top level design file, connect the signals in the DisplayPort TX sub-system as shown below.
Figure 7. Video PLL with Tx_vid_clk outputNote: The CVO II and TPG II Intel® FPGA IPs share the reset input from the reset generator output (reset_n), through VIP Reset Bridge.
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