AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.5.6. Modifying the Software

After removing the irrelevant blocks and reconnecting the remaining blocks with the newly instantiated FPGA IPs, modify the software.
  1. First, modify the software's config.h file. Navigate to the design example folder and change the values of the following parameter settings in the file.
    Table 10.  Config.h Parameter Settings
    Parameter Value Description
    BITEC_AUX_DEBUG 0 Set to 1 to enable AUX channel traffic monitoring.
    BITEC_STATUS_DEBUG 1 Set to 1 to enable MSA and link status monitoring.
    DP_SUPPORT_RX 0 Set to 1 if the DisplayPort supports RX.
    BITEC_RX_GPUMODE 0 Set to 1 to enable Sink GPU mode.
    BITEC_RX_CAPAB_MST 0 Set to 1 to enable MST support.
    BITEC_RX_FAST_LT_SUPPORT 0 Set to 1 to enable Fast Link Training support.
    BITEC_RX_LQA_SUPPORT 0 Set to 1 to enable Link Quality Analysis support.
    BITEC_EDID_800X600_AUDIO 0 Set to 1 to use an EDID with maximum resolution 800 x 600
    BITEC_DP_0_AV_RX_CONTROL_BITEC_CFG_RX_SUPPORT_MST 0 Set to 1 to enable MST support
    DP_SUPPORT_TX 1 Set to 1 if DisplayPort supports TX
    BITEC_TX_CAPAB_MST 0 Set to 1 to enable MST support
    TX_VIDEO_IM_ENABLE 0 Set to 1 to enable TX Video IM interface
    DP_SUPPORT_EDID_PASSTHRU 0 Set to 1 to enable EDID passthrough from sink to source.
    BITEC_DP_CARD_REV 0
    • Set to 0 = Bitec FMC DisplayPort daughter card revision 4 – 8 (without Paradetech Retimer)
    • Set to 1 = Bitec FMC DisplayPort daughter card revision 9 or later (with Paradetech Retimer)
    MST_RX_STREAMS 0 RX MST number of streams
    MST_TX_STREAMS 0 TX MST number of streams
    Note: You must select a correct Bitec FMC DisplayPort daughtercard revision. Make the selection in the Config.h and design top level file.
  2. Since DisplayPort TX-only design does not require a retimer at RX, remove below code in the software/dp_demo/Main.c. 
    #if (BITEC_DP_CARD_REV == 1)
  // Bitec Daughter Card Rev 10
  // Init the PS8460 I2C interface
  intel_fpga_i2c_init(I2C_MASTER_BASE, 100000000);

  // Set the PS8460 P4 registers
  // Set the PS8460 equaliser as required by your design
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x09, 0x02);
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0B, 0xC4); // Enable EQ from I2C register,squelch enabled
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0C, 0x55); // HBR RBR EQ
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0D, 0x85); // HBR2 EQ
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x0E, 0x05); // HBR3 EQ
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9A, 0x88); // L1_VOD L1_PRE L0_VOD L0_PRE
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0x9B, 0x88); // L3_VOD L3_PRE L2_VOD L2_PRE
  intel_fpga_i2c_write_extended(I2C_MASTER_BASE, 0x18 >> 1, 0xA4, 0x08); // Full Jitter cleaning mode
#endif

#if (BITEC_DP_CARD_REV == 2)
  // Bitec Daughter Card Rev 11
  unsigned int data;

  // Init the MCDP6000 on the Bitec Sink main link input
  // (on the Bitec daughter board)
  // Set the MCDP6000 as required by your design
  
  intel_fpga_i2c_init(I2C_MASTER_BASE, 100000000);  

  data = 0x0001704E; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0504, (unsigned char *)&data, 4);
  data = 0x00000601; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x01D8, (unsigned char *)&data, 4);
  data = 0x00005011; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0660, (unsigned char *)&data, 4);
  data = 0x00000001; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x067C, (unsigned char *)&data, 4);
  data = 0x55801E14; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0A00, (unsigned char *)&data, 4); // MC solution #2
  data = 0x0000001F; intel_fpga_i2c_mc_write(I2C_MASTER_BASE, 0x28 >> 1, 0x0350, (unsigned char *)&data, 4); // MC solution #3

#endif
  3. In the Intel® Quartus® Prime Pro Edition software, the bitec_dptx_init() function is only called when DP_SUPPORT_EDID_PASSTHRU is enabled in Config.h. Since DP_SUPPORT_EDID_PASSTHRU is not needed for this design, DP TX will never get initialized. To avoid this, bring out the bitec_dptx_init() function from the #if DP_SUPPORT_EDID_PASSTHRU directive so that the function can run. For example: 
    // Init Bitec DP system library
#if DP_SUPPORT_TX
  btc_dptx_syslib_add_tx(0,
  		 DP_TX_DP_SOURCE_BASE,
                         DP_TX_DP_SOURCE_IRQ_INTERRUPT_CONTROLLER_ID,
                         DP_TX_DP_SOURCE_IRQ);
  btc_dptx_syslib_init();
  bitec_dptx_init(); 
#endif
  4. Remove the bitec_dp_dump_sink_msa() and bitec_dp_dump_sink_config() from the Main.c.
  5. Next, for debugging purposes, modify the debug.c file located in the software/dp_demo folder. Open the debug.c file and remove the void bitec_dp_dump_sink_msa() and void bitec_dp_dump_sink_config() functions.
    Note: Any modifications you make in the debug.c and Main.c, the script will be overwritten each time you rebuild the software. To prevent this, place a copy of the modified Main.c and debug.c file in the main software folder before you rebuild your software.
  6. In a Nios II Command Shell, cd into the script directory and ‘source build_sw.sh’ to update software. The updated dp_demo.elf file is located in the software/dp_demo directory.
    Note:
    • After you make any change to the software (ie: config.h or any other software file), you must run build_sw.sh script from a nios2-terminal to ensure the software (dp_demo.elf) file is accurate.
    • The IP components in the Platform Designer are utilized in the generation of the BSP (Board Support Package). For this reason, it is also imperative to regenerate software if you make any changes or updates within the Platform Designer dp_core system as well.
    • If design has already been compiled and a10_dp_demo.sof image previously generated, load dp_demo.elf from a nios2 command shell and run ‘nios2-download dp_demo.elf’ in the Nios terminal. Use push button reset on the Intel® Arria® 10 GX development kit for software changes to take effect.
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