AN 883: Intel Arria 10 DisplayPort TX-only Design

ID 683597
Date 7/03/2021

1.5.1. Generating the Design

Before you make the modifications, first you need to generate the DisplayPort SST Parallel Loopback design example in the Intel® Quartus® Prime Pro Edition.
  1. Instantiate the DisplayPort Intel® FPGA IP and specify the parameters.
    Table 6.  Example of IP Parameters Value to Generate a 4kp60 Output Video
    Parameters Value Description
    Maximum video output color depth (Source) 10 bpc This design supports GPU and monitors up to a maximum of 10 bit-per-color depth.
    Maximum link rate 5.4 Gbps The bandwidth requirement for 4Kp60 and 10 bpc video stream through serial link:
    • Active video resolution = 3840 × 2160 pixels/frame
    • Total resolution (including reduced blanking) = 4000 × 2222 pixels/frame
    • Refresh rate = 60 Hz or 60 frames per second
    • Bits per pixel = 10 bpc × 3 colors = 30 bits per pixel
    • Total bandwidth = (4000 × 2222) pixel/frame × 60 frame/s × 30 bits/pixel = 15.9984 Gbits/s
    With 8b/10b encoding scheme, the actual bandwidth required = 15.9984 × 10/8 = 19.998 Gbps. With 4 lanes at 5.4 Gbps, the aggregated bandwidth of 21.6 Gbps is sufficient to support the 4K video stream at 60 Hz refresh rate.
    Maximum lane count 4
    Symbol output mode (Source) Quad

    Symbol mode affects the transceiver parallel bus width and the DisplayPort IP core clock frequency. The DisplayPort IP core synchronizes with the transceiver parallel clock. The parallel clock frequency is link rate/transceiver parallel bus width.

    Frequency for HBR2 (5.4 Gbps) is 5400/20 or 270 MHz for dual (20 bits) and 5400/40 or 135 MHz for quad (40 bits) mode.
    Symbol input mode (Sink)
    Pixel input mode (Source) Quad

    Pixel mode affects the video clock frequency and video port width of the IP core.

    For 4Kp60 video stream, the bandwidth requirement is 4000 × 2222 × 60 pixel/s = 533280000 pixels/s. Because of the high bandwidth requirement, the design requires dual or quad pixel mode for timing closure.

    • Single (1 pixel/clock) 533.28 MHz
    • Dual (2 pixels/clock) 266.64 MHz
    • Quad (4 pixels/clock) 133.32 MHz
    Pixel output mode (Sink)
    Support analog reconfiguration On Enable analog reconfiguration interface. Used to reconfigure vod and pre-emphasis value.
    Enable AUX debug stream On Enable AUX source traffic output to Avalon-ST port
    DisplayPort SST Parallel Loopback With PCR On Enable Pixel Clock Recovery in the design.
    Note: The table above is an example of IP setting. However, Intel recommends you to generate a base example design with required IP setting (BPC, symbol per clock, pixel per clock, number of channels, link rate) and then proceed with the design modification. Changing the IP settings at the later stage can cause design conflict if not done properly.
  2. Click Generate Example Design with Intel® Arria® 10 GX FPGA Development kit as a target board.

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