CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Document Table of Contents

3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces

The CPRI Intel® FPGA IP configures the interface to the CPRI serial link in an Intel® FPGA device transceiver channel. The IP core provides multiple interfaces for managing the transceiver. The transceiver is configured with a Native PHY IP core and exposes many of its optional interfaces for ease of IP core integration in your design. The transceiver and transceiver management interfaces are used for calibration of the TX PLL and PHYs. Refer to the Transceiver PLL Calibration for more information.

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