CPRI Intel® FPGA IP User Guide

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ID 683595
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers 6. CPRI Intel® FPGA IP User Guide Archives 7. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. System PLL Connections for the Intel Agilex® 7 F-tile Variations 2.5.3. Adding the Reset Controller 2.5.4. Adding the Transceiver Reconfiguration Controller 2.5.5. Adding the Off-Chip Clean-Up PLL 2.5.6. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.7. Transceiver PLL Calibration 2.5.8. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
6. CPRI Intel® FPGA IP User Guide Archives
7. Document Revision History for the CPRI Intel® FPGA IP User Guide

2.5.3. Adding the Reset Controller

The CPRI Intel® FPGA IP core requires that you provide reset control logic to handle the required reset sequence for the IP core transceiver on the device. For a duplex CPRI IP core, you must generate and connect two Transceiver PHY Reset Controller IP cores to perform this function, one reset controller for the TX transceiver and one reset controller for the RX transceiver in the CPRI IP. If you do not implement the device-specific transceiver reset sequence, the IP core does not function correctly in hardware.

You can use the IP Catalog to generate Transceiver PHY Reset Controller IP cores for the device family that your CPRI IP core targets.

The CPRI IP core configures the Native PHY IP core for the target device family. You must configure the reset controllers to coordinate reset of the CPRI IP core including the Native PHY IP core, and the transceiver PLL IP core. In the case of Arria V, Arria V GZ, Cyclone V, and Stratix V variations, the reset controllers must also coordinate with the transceiver reconfiguration controller. Refer to the device specific PHY user guide for more information.

The CPRI IP core that target an Intel® Stratix® 10 E-tile or Intel Agilex® 7 E- tile device uses the embedded reset controller and do not require external reset controller.

To configure a TX reset controller, in the Transceiver PHY Reset Controller parameter editor, you must set the following parameter values:

  • Set Input clock frequency to a value in the range of 100–150 MHz. You must drive the CPRI IP reconfig_clk at the same frequency you specify for this parameter.
  • Turn on Synchronize reset input.
  • Turn on Use fast reset for simulation.
  • Turn on Enable TX PLL reset control.
  • Set pll_powerdown duration to the value of 10.
  • Turn on Enable TX channel reset control.
  • Leave all other parameters turned off or for the parameters that do not turn on or off, at their default values.

To configure an RX reset controller, in the Transceiver PHY Reset Controller parameter editor, you must set the following parameter values:

  • Set Input clock frequency to a value in the range of 100–150 MHz. You must drive the CPRI IP reconfig_clk at the same frequency you specify for this parameter.
  • Turn on Synchronize reset input.
  • Turn on Use fast reset for simulation.
  • Turn on Enable RX channel reset control.
  • Leave all other parameters turned off or for the parameters that do not turn on or off, at their default values.

You must connect the external reset controller signals to the CPRI IP core reset controller interface signals and transceiver TX PLL signals according to the following rules. Refer to Integrating Your Intel FPGA IP Core in Your Design: Required External Blocks for an illustration of the connections.

Table 14.  Required Connections to and From Reset Controllers in CPRI DesignLists the required connections between the reset controllers and the CPRI IP and the transceiver TX PLL IP core. For information about connecting the transceiver TX PLL to the CPRI IP, refer to Adding the Transceiver TX PLL IP Core.
Transmit-Side Reset Controller Signal Connect to
clock (input) Clock source for CPRI IP reconfig_clk input signal
reset (input) Source of CPRI IP reset_tx_n input signal, inverted
pll_powerdown (output) TX PLL pll_powerdown
pll_locked (input) TX PLL pll_locked
tx_analogreset (output) CPRI IP xcvr_tx_analogreset
tx_digitalreset (output) CPRI IP xcvr_tx_digitalreset
tx_cal_busy (input) CPRI IP xcvr_tx_cal_busy
tx_ready (output) CPRI IP xcvr_reset_tx_ready
Receive-Side Reset Controller Signal Connect to
clock (input) Clock source for CPRI IP reconfig_clk input signal
reset (input) Source of CPRI IP reset_rx_n input signal, inverted
rx_is_lockedtodata (input) CPRI IP xcvr_rx_is_lockedtodata
rx_analogreset (output) CPRI IP xcvr_rx_analogreset
rx_digitalreset (output) CPRI IP xcvr_rx_digitalreset
rx_cal_busy (input) CPRI IP xcvr_rx_cal_busy
rx_ready (output) CPRI IP xcvr_reset_rx_ready

User logic must provide the connections. Refer to the demonstration testbench for example working user logic including one correct method to instantiate and connect the external reset controllers. Refer to the Figure 1 diagram to see the connections.

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