126.96.36.199. Tx Bitslip Delay
The CPRI Intel® FPGA IP core reports the Rx bitslip through the word aligner in the rx_bitslip_out field of the XCVR_BITSLIP register, and compensates for the variable delay by adding a bitslip in the Tx path. The current size of this bitslip in bits is available in the tx_bitslip_in field of the XCVR_BITSLIP register. When you leave the tx_bitslip_en field at its default value of 0, this feature is active.
The Tx bitslip feature ensures stability in the round-trip delay through a CPRI RE core, but introduces a variable component in each of the Tx and Rx paths when considered independently. In CPRI IP cores in master clocking mode, the rx_bitslip_out field has the constant value of 0.
If you set the value of the tx_bitslip_en field to 1, you can override the current rx_bitslip_out value to control the Tx bitslip delay manually. Intel® does not recommend implementing the manual override.
In CPRI IP variations that target an Arria V, Cyclone V, or Stratix V device, the Tx bitslip functionality is included in the Transceiver PHY Intel® FPGA IP core that is generated with the CPRI Intel® FPGA IP. These variations include the XCVR_BITSLIP register to support manual override of the Tx bitslip delay.
The total of the Tx bitslip delay and the word aligner bitslip delay in the transceiver receiver is added to the detailed round-trip delay calculation as part of the Tx and Rx transceiver delays. However, the total of these two bit values does not reach the duration of a single cpri_clkout cycle, nor does it reach the threshold of the CPRI specification R-20 and R-21 requirements. The bitslip delay is noticeable only with an oscilloscope.
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