CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Public

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3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface

This interface is available only if you turn on at least one of these parameters in the CPRI parameter editor:

  • Enable line bit rate auto-negotiation
  • Enable start-up sequence state machine
Table 45.  Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface SignalsAll interface signals are clocked by the reconfig_clk clock.

Signal Name

Direction

Description

reconfig_clk Input Clock for CPRI IP transceiver start-up and reconfiguration. The frequency range for this clock is 100–150 MHz.
reconfig_reset Input Asynchronous active-high reset signal for transceiver start-up and reconfiguration. Used for rate switching and auto-rate negotiation.
reconfig_to_xcvr[69:0] Input Parallel transceiver reconfiguration bus from the Transceiver Reconfiguration Controller to the transceiver in the CPRI IP.
reconfig_from_xcvr[45:0] Output Parallel transceiver reconfiguration bus to the Transceiver Reconfiguration Controller from the transceiver in the CPRI IP.