CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Document Table of Contents

4. CPRI Intel® FPGA IP Core Signals

The CPRI IP core communicates with the surrounding design through multiple external signals. Many of the signal interfaces are optional; their presence or absence depends on whether or not you enable the corresponding interface in the CPRI parameter editor.

In the case of the interfaces that provide direct access to all or part of the CPRI frame, write transmit delay relative to the AUX TX interface synchronization signals depends on the Auxiliary and direct interfaces write latency cycle(s) parameter setting.

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