CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.18.3.1. Rx Path Delay

The Rx path delay is the cumulative delay from the arrival of the first bit of a 10 ms radio frame on the CPRI Rx interface to the start of transmission of the radio frame on the AUX interface.
Figure 60. Rx Path Delay to AUX Output in CPRI Intel® FPGA IP

The Rx path delay to the AUX interface is the sum of the following delays:

  1. The link delay is the delay between the arrival of the first bit of a 10 ms radio frame on the CPRI Rx interface and the CPRI IP internal transmission of the radio frame pulse from the CPRI protocol interface receiver.
    1. Rx transceiver latency is a fixed delay through the deterministic latency path of the Rx transceiver. Its duration depends on the device family and the current CPRI line bit rate. This delay includes comma alignment and byte alignment within the transceiver.
    2. Fixed delay from the Rx transceiver to the Rx elastic buffer. This delay depends on the device family and the CPRI line bit rate.
      Note: In IP core variations that target an Intel® Stratix® 10 device, you must also add the delay through the Stratix 10 hard FIFOs in the Rx path.
    3. Delay through the clock synchronization FIFO, as well as the phase difference between the recovered receive clock and the core clock cpri_clkout. The "Extended Delay Measurement" section shows how to calculate the delay in the CPRI IP core Rx elastic buffer, which includes the phase difference delay.
    4. Byte alignment delay that can occur as data is shifted out of the receiver. This variable delay appears in the rx_byte_delay field of the RX_DELAY register. When the value in rx_byte_delay is non-zero, a byte alignment delay of one cpri_clkout cycle occurs in the Rx path.
    5. Variable delay introduced by the optional single-trip delay calibration feature in CPRI link slave IP cores.
    6. Variable delay introduced by the optional round-trip delay calibration feature in CPRI link master IP cores.
  2. Delay from the CPRI low-level receiver block to the AUX interface. This delay depends on the device family and the CPRI line bit rate.