5. CPRI Intel® FPGA IP Core Registers
All of these registers are 32 bits wide and the addresses are shown as hexadecimal byte address values. The registers can be accessed on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.
Write access to a Reserved or undefined location has no effect. Read accesses to a Reserved or undefined location return an undefined result.
Refer to the device specific PHY User Guides for information about the PHY registers.
|RW||Read / write|
|RC||Read to clear|
|UR0||Reserved —undefined result on read, no effect on write|
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