Visible to Intel only — GUID: nik1411442168856
Ixiasoft
Visible to Intel only — GUID: nik1411442168856
Ixiasoft
3.10. Direct HDLC Serial Interface
This interface is Avalon-ST compliant with a ready latency value of 1.
You can alter the transmit write latency with the Auxiliary and direct interfaces write latency cycle(s) parameter. However, you do not need to view the aux_tx_seq signal for correct alignment. You can monitor the hdlc_rx_valid and hdlc_tx_ready signals to discover the correct times to read and write data on this interface.
Direct HDLC Serial RX Interface | ||
---|---|---|
Signal Name |
Direction |
Description |
hdlc_rx_valid | Output | When asserted, indicates hdlc_rx_data holds a valid HDLC bit in the current clock cycle. |
hdlc_rx_data | Output | HDLC data stream received from the CPRI frame. The hdlc_rx_valid signal indicates which bits are valid HDLC bytes. |
Direct HDLC Serial TX Interface | ||
Signal Name |
Direction |
Description |
hdlc_tx_ready | Output | When asserted, indicates the IP core is ready to receive HDLC data from hdlc_tx_data on the next clock cycle. |
hdlc_tx_valid | Input | Write valid for hdlc_tx_data. Assert this signal to indicate that hdlc_tx_data holds a valid HDLC bit in the current clock cycle. |
hdlc_tx_data | Input | HDLC data stream to be written to the CPRI frame directly. The IP core writes the current value on hdlc_tx_data to the CPRI frame based on the hdlc_tx_ready signal from the previous cycle, and the hdlc_tx_valid signal in the current cycle. |
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