CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Document Table of Contents

3.19.7. Interface to the External PLL

Table 49.   CPRI Intel® FPGA IP Core External PLL Interface SignalsThe CPRI Intel® FPGA IP requires that you generate and connect an external transceiver PLL IP core. This signal is not available in Intel® Stratix® 10 E-tile and Intel Agilex® 7 E- tile device variations since the PHY includes the transceiver PLL.

Signal Name



xcvr_ext_pll_clk Input

Clocks the transmitter PMA.

You should drive this input clock with the output of the external transceiver TX PLL. In Arria 10 devices, you have a choice of different TX PLL IP cores to configure. You must ensure that you configure a PLL IP core that is capable of driving the frequency that the CPRI IP core requires to run at the specified CPRI line bit rate.

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