CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/19/2023
Document Table of Contents Single-Trip Latency Measurement and Calibration Interface Signals

Table 42.  Single-Trip Latency Measurement and Calibration Interface SignalsIf you turn on Enable single-trip delay calibration in the CPRI parameter editor, the single-trip latency measurement and calibration interface is available. This interface is designed to connect to the DPCU block that helps implement single-trip delay calibration.

All interface signals are clocked by the reconfig_clk clock.

Signal Name



cal_status[1:0] Input Status information from DPCU to CPRI IP core.
cal_ctrl[15:0] Output Control information from CPRI IP core to DPCU.

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