Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

ID 683572
Date 10/31/2022

Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Document Version Changes
2022.10.31 Added 1.8 V LVDS I/O standard support.
2022.01.27 Updated the spreadsheet files ( that list the mutual inductance values for 1.0 V I/O.
2021.11.01 Added F256 device package and updated U324 device package in the DDR3 and LPDDR2 Memory Interface Widths and Device Packages Where Two GPIOs Adjacent to DQ Pins Are Disabled table.
2021.04.27 Updated the guidelines in the table listing the geometry-based I/O restrictions related to ADC usage.
  • Updated the clamp diode for LVTTL/LVCMOS input buffers guidelines to remove references to "undershoot". The clamp diode manages overshoot voltages only.
  • Updated the table in the I/O restriction rules guideline topic to improve clarity.
  • Added 1.0 V LVCMOS I/O standard.
  • Added placement restriction guideline for 1.0 V I/O pins.
Date Version Changes
December 2017 2017.12.15
  • Updated the description in the guideline topic about I/O restrictions to improve clarity.
  • Updated the guideline topic about the clock and data input signal for the E144 package to improve clarity.
  • Updated the guideline topic about the ADC I/O restriction to clarify that the guidelines are geometry-based rules for design estimation purpose.
  • Updated the guideline topic about enabling the clamp diode for the LVTTL/LVCMOS input buffers to improve clarity.
March 2017 2017.03.02 Added a note to the guideline about the data input pin to specify that the signal to the input pin must be 1.5 V/ns or faster if an adjacent pin operates as a toggling output.
February 2017 2017.02.21 Rebranded as Intel.
November 2015 2015.11.02
  • Added recommendation about instantiating the input clock signal with full rail voltage in Guidelines: Clock and Asynchronous Control Input Signal.
  • Added a new topic: Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
  • Updated the description in the Maximum Percentage of I/O Pins Allowed for Specific I/O Standards in an I/O Bank table in Guidelines: I/O Restriction Rules.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.11
  • Added recommendation about not using unterminated I/O standards in the same bank as the input clock signal to the PLL.
  • Updated the board design guidelines for analog input.
  • Updated the ADC I/O restriction guidelines topic.
May 2015 2015.05.04
  • Updated the guidelines for voltage-referenced I/O standards to add a list of device packages that do not support voltage-referenced I/O standards.
  • Updated the topic about the I/O restriction rules to remove statements about the differential pad placement rules.
  • Updated the topic about external memory interface I/O restrictions to add x24 memory interface width to the F484 package.
  • Removed statements about availability of the threshold trigger feature in a future version of the Intel® Quartus® Prime software. The feature is now available from version 15.0 of the software.
  • Updated the RC constant and filter value and the filter design example figure to clarify the source of the example values.
  • Removed notes about contacting Intel for the ADC pin RLC filter design.
  • Updated the guidelines about board design requirement for DDR2, DDR3, and LPDDR2 to improve clarity.
December 2014 2014.12.15 Initial release.