Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
ID
683532
Date
8/05/2019
Public
2.2.1.1. Clocks in 4x10GBASE-SR Mode
2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode
2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode
2.2.1.4. PR Management in 4x10GBASE-SR Mode
2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode
2.2.1.6. Initialization in 4x10GBASE-SR Mode
2.2.1.7. Unused 10GbE Channels
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings
3.1.4.2. Receiver VGA sysfs Encodings
3.1.4.3. Receiver CTLE DC Gain sysfs Encodings
3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings
3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings
3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings
3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings
3.1.4.8. Transmitter VOD Encodings
3.2.1. Configuring the Network Port
To enable the network port, you must configure the HSSI PHY mode and load a network port-enabled AF from the host. The following procedure shows the programming method for 4x10GBASE-SR operation from a shell terminal window using Linux commands and OPAE tools for a single Intel® PAC with Intel® Arria® 10 GX FPGA installed in the system.
- Configure the HSSI PHY on the Intel® PAC with Intel® Arria® 10 GX FPGA using the driver config sysfs file.
$ sudo sh -c “echo 10 > \ /sys/class/fpga/intel-fpga-dev.<i>/intel-fpga-fme.<j>/intel-pac-hssi.<m>.auto/hssi_mgmt/config”
- Load an AF that supports the configured HSSI PHY mode.
$ sudo fpgaconfig \ $OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e10/bin/eth_e2e_e10.gbs
After performing the above steps, the network port on the Intel® PAC with Intel® Arria® 10 GX FPGA is ready for OPAE applications compatible with the loaded AF.