Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 2/10/2023
Document Table of Contents

2.3.3. Resets

  • Turning on the Enable HPS warm reset handshake signals option enables an additional pair of reset handshake signals allowing soft logic to notify the HPS when it is safe to initiate a warm reset in the FPGA fabric. Turning on this option exposes the h2f_warm_reset_handshake conduit, which is comprised of the signals h2f_pending_rst_req_n and f2h_pending_rst_ack_n.
  • Turning on the Enable HPS-to-FPGA cold reset output option exposes the h2f_cold­reset reset output interface. This signal is asserted when the HPS undergoes a cold reset.
  • Turning on the Enable watchdog reset option exposes the h2f_watchdog_rst reset output interface and is asserted when the HPS watchdog timers are triggered.
  • The How SDM handles HPS watchdog reset dropdown provides an input to the compiled bitstream that directs the SDM to treat the HPS watchdog reset assertion as an HPS Cold reset, HPS warm reset, or Trigger Remote Update.