3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
220.127.116.11. Running HPS Post-Fit Simulation
To run HPS post-fit simulation after successful Platform Designer generation, perform the following steps:
- Add the generated synthesis file set to your Intel® Quartus® Prime project by performing the following steps:
- In the Intel® Quartus® Prime software, click Settings in the Assignments menu.
- In the Settings <your Platform Designer system name> dialog box, on the Files tab, browse to <your project directory>/<your Platform Designer system name> /synthesis/ and select <your Platform Designer system name> .qip.
- Click Open. The Select File dialog box closes.
- Click OK. The Settings dialog box closes.
- Optionally instantiate your HPS system as the top-level entity in your Intel® Quartus® Prime project.
- Compile the design by clicking Start Compilation in the Processing menu.
- Change the EDA Netlist Writer settings, if necessary, by performing the following steps:
- Click Settings in the Assignment menu.
- On the Simulation tab, under the EDA Tool Settings tab, you can specify the following EDA Netlist Writer settings:
- Tool name—The name of the simulation tool
- Format for output netlist
- Output directory
- Click OK.
- To create the post-fitter simulation model with Intel® Quartus® Prime EDA Netlist Writer, perform the following steps:
- Click Start in the Processing menu.
- Click Start EDA Netlist Writer.
Post-Fit Simulation Files
BFM API Hierarchy Format
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