Intel® Stratix® 10 Hard Processor System Component Reference Manual

ID 683516
Date 2/10/2023
Document Table of Contents

3.8. HPS-to-FPGA Debug APB Interface

The HPS-to-FPGA debug APB interface is connected to an Intel® conduit BFM for simulation. The following table lists the name of each interface, along with API function names for each type of simulation. You can monitor the interface state changes or set the interface by using the API functions listed.

Table 26.  HPS-to-FPGA Debug APB Interface Simulation Model

Interface Name

BFM Name

RTL Simulation API Function Names

Post-Fit Simulation API Function Names



set_h2f_dbg_apb_PADDR() set_PADDR()
set_h2f_dbg_apb_PADDR_31() set_PADDR_31()
set_h2f_dbg_apb_PENABLE() set_PENABLE()
get_h2f_dbg_apb_PRDATA() get_PRDATA()
get_h2f_dbg_apb_PREADY() get_PREADY()
set_h2f_dbg_apb_PSEL() set_PSEL()
get_h2f_dbg_apb_PSLVERR() get_PSLVERR()
set_h2f_dbg_apb_PWDATA() set_PWDATA()
set_h2f_dbg_apb_PWRITE() set_PWRITE()



get_h2f_dbg_apb_PCLKEN() get_PCLKEN()
get_h2f_dbg_apb_DBG_APB_DISABLE() get_DBG_APB_DISABLE()