3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
1.4. FPGA Bridges
The FPGA bridges provide a variety of communication channels between the HPS and the FPGA fabric. The HPS is highly integrated with the FPGA fabric, resulting in thousands of connecting signals. Some of the HPS-to-FPGA interfaces include:
- FPGA-to-HPS bridge
- HPS-to-FPGA bridge
- Lightweight HPS-to-FPGA bridge
- FPGA-to-HPS SDRAM bridge
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