Intel® Stratix® 10 Hard Processor System Component Reference Manual
ID
683516
Date
2/10/2023
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the HPS Component Revision History
3.2.2. Reset Interface
The HPS reset request and handshake interfaces are connected to Intel® conduit BFMs for simulation.
Interface Name |
BFM Instance Name |
API Function Names |
---|---|---|
h2f_warm_reset_handshake | h2f_warm_reset_handshake_inst | set_h2f_pending_rst_req_n() |
get_f2h_pending_rst_ack_n() |
Interface Name |
BFM Instance Name |
---|---|
h2f_reset | h2f_reset_inst |
h2f_cold_reset | h2f_cold_reset_inst |
h2f_debug_apb_reset | h2f_debug_apb_reset_inst |
Parameter |
BFM Value |
Meaning |
---|---|---|
Assert reset high |
Off |
This parameter is off, specifying an active‑low reset signal from the BFM. |
Cycles of initial reset |
0 |
This parameter is 0, specifying that the BFM does not assert the reset signal automatically. |
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