3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component
|Intel® Quartus® Prime Design Suite 22.4|
The hard processor system (HPS) component is a wrapper that interfaces logic in your design to the:
- HPS hard logic
- Simulation models
- Bus functional models (BFMs)
- Software handoff files
After you connect the soft logic to the HPS, you can use Platform Designer to ensure the following features:
- Interoperability by adapting Avalon® Memory-Mapped ( Avalon® -MM) interfaces to AXI*
- Handling of data width mismatches and clock domain transfer crossings
You are able to integrate Intel® FPGA IP, 3rd party IP, and custom IP that you define into the HPS without creating integration logic. This reference manual details the interfaces exposed and configured by the options in the component.
For more information about the HPS system architecture and features, refer to the "Introduction to the Hard Processor" chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.
Cortex-A53 MPCore Processor
CoreSight Debug Components
Introduction to the HPS Component Revision History
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