Intel® Stratix® 10 Hard Processor System Component Reference Manual
ID
683516
Date
2/10/2023
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the HPS Component Revision History
2.3.2.1. Main PLL Output Clocks – Desired Frequencies
This section allows you to control the MPU clock frequency. The Default MPU clock frequency field displays the default maximum frequency for the MPU based on the device speed grade selected, and the input voltage selected in the VCCL_HPS Value dropdown. You may check the Override default MPU clock frequency box to manually enter a slower frequency than the default MPU clock frequency, in the Custom MPU clock frequency field.
For more information about the maximum MPU clock frequencies, refer to the Intel Stratix 10 Device Datasheet.
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