3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
188.8.131.52. HPS to FPGA AXI-4 Master Interface
The HPS-to-FPGA AXI* -4 Master interface allows HPS masters to issue transactions to the FPGA fabric. You can use the:
- Enable/Data Width dropdown to configure this master interface's data widths to 32-, 64-, or 128-bit.
- Ready Latency pipeline dropdown configures the flexible ready latency pipelining available in the FPGA fabric. This can assist with timing closure at the FPGA-to-HPS boundary and is configurable to depths of 0 (none), 1, 2, 3, or 4.
- Bridge address width is configurable from 32 bits down to 20 bits. When this bridge is enabled, the interfaces h2f_axi_master, h2f_axi_clock, and h2f_axi_reset are made available.
This bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally. The exposed AXI* interface operates on the same clock domain as the clock supplied by the FPGA fabric. Other interface standards in the FPGA fabric, such as connecting to Avalon® -MM interfaces, can be supported through the use of soft logic adapters. The Platform Designer system integration tool automatically generates adapter logic to connect AXI* to Avalon® -MM interfaces.
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