Visible to Intel only — GUID: rwa1481912674990
Ixiasoft
Visible to Intel only — GUID: rwa1481912674990
Ixiasoft
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
The lightweight HPS‑to‑FPGA AXI* master interface, h2f_lw_axi_master, is connected to a Mentor Graphics AXI* master BFM for simulation with an instance name of h2f_lw_axi_master_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to h2f_lw_axi_clock clock.
Parameter |
Value |
---|---|
AXI* Address Width |
20 - 21 |
AXI* Read and Write Data Width |
32 |
AXI* ID Width |
4 |
You control and monitor the AXI* master BFM by using the BFM API.
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