3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
2.7. Generating and Compiling the HPS Component
The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer project. Perform the following steps:
- Generate the design with Platform Designer. The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
- Add <qsys_system_name>.qip to the Intel® Quartus® Prime project. <qsys_system_name>.qip is the Intel® Quartus® Prime IP File for the HPS component, generated by Platform Designer.
Note: Platform Designer generates pin assignments in the .qip file.
- Perform analysis and synthesis with the Intel® Quartus® Prime software.
- Compile the design with the Intel® Quartus® Prime software.
- Optionally back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.
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