2.8. Using the Address Span Extender Component
The FPGA-to-HPS bridge and FPGA-to-HPS SDRAM bridge memory-mapped interfaces can be configured to expose their entire address spaces to the FPGA fabric, 132GB and 128GB, respectively. The address span extender component provides a memory-mapped window into the address space that it masters. Using the address span extender, an FPGA master with a smaller address span can access the entire address space exposed by the FPGA bridge.
You can use the address span extender between a soft logic master and an FPGA-to- HPS bridge or FPGA-to-HPS SDRAM interface. This component reduces the number of address bits required for a master to address a memory-mapped slave interface located in the HPS.
In the example shown in the figure below, the bridges in the HPS component are configured for 32-bit wide addresses (4GB address span).
You can also use the address span extender in the HPS-to-FPGA direction, for slave interfaces in the FPGA. In this case, the HPS-to-FPGA bridge exposes a limited, variable address space in the FPGA, which can be paged in using the address span extender.
For example, suppose that the HPS-to-FPGA bridge has a 1-GB span, and the HPS needs to access three independent 1-GB memories in the FPGA portion of the device. To achieve this, the HPS programs the address span extender to access one SDRAM (1-GB) in the FPGA at a time. This technique is commonly called paging or windowing.
For more information about the Intel Span Extender, refer to the Address Span Extender section in the Intel® Quartus® Prime Pro Edition User Guide: Platform Designer.
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