V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

Read DMA and Write DMA modules report status to the Descriptor Controller on the RdDmaTxData_o[31:0] or WrDmaTxData_o[31:0] bus when a descriptor completes successfully.

The following table shows the mappings of the triggering events to the DMA descriptor status bus:

DMA Status Bus

Bits

Name

Description

[31:9]

Reserved

[8]

Done

When asserted, a single DMA descriptor has completed successfully.

[7:0] Descriptor ID The ID of the descriptor whose status is being reported.

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