V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

Cyclone V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate the placement of the PCIe IP cores, transceiver banks, and channels. Note that the bottom left IP core includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality. Transceiver banks include six channels. Within a bank, channels are arranged in 3-packs. GXB_L0 contains channels 0–2, GXB_L1 includes channels 3–5, and so on.
Cyclone V GX/GT/ST/ST Devices with 9 or 12 Transceiver Channels and 2 PCIe CoresIn the following figure, the x1 Hard IP for PCI Express uses channel 0 and channel 1 of GXB_L0 and channel 0 and channel 1 of GXB_L2.
Cyclone V GX/GT/ST/ST Devices with 6 Transceiver Channels and 2 PCIe Cores
For more comprehensive information about Cyclone V transceivers, refer to the Transceiver Banks section in the Transceiver Architecture in Cyclone V Devices.

Did you find the information on this page useful?

Characters remaining:

Feedback Message