V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

Arria V GZ devices include one Hard IP for PCI Express IP core. The following figures illustrate the placement of the PCIe IP core, transceiver banks, and channels.
Physical Layout of Hard IP in Arria V GZ Devices

Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of Hard IP for PCIe IP cores available in various Arria V GZ packages.

Refer to Channel Utilization for Data and Clock Routing in Arria V GZ and Stratix V Devices for additional information about channel and PLL utilization.

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