V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

Arria V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate the placement of the PCIe IP core, transceiver banks, and channels.

Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files for Intel Devices.

Arria V devices include one or two Hard IP for PCI Express IP Cores. The following figures illustrates the placement of the Hard IP for PCIe IP cores, transceiver banks and channels for the largest Arria V devices. Note that the bottom left IP core includes the CvP functionality. Devices with a single Hard IP for PCIe IP Core only include the bottom left core.

Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria GX and GT Devices
Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria SX Devices
Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria ST Devices

Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of Hard IP for PCIe IP cores available in various Arria V packages.

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