V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

ID 683514
Date 7/31/2018
Public
Document Table of Contents

When DMA module completes the processing for one Descriptor Instruction, it returns DMA Status to the Descriptor Controller via the following interfaces.

Read DMA Status Interface from Read DMA Engine to Descriptor Controller

Signal Name

Direction

Description

RdAstTxData_o[31:0]

Output

Drives status information to the Descriptor Controller component. Refer to DMA Status Bus table below for more information

RdAstTxValid_o

Output

When asserted, indicates that the data is valid.

Write DMA Status Interface from Write DMA Engine to Descriptor Controller

Signal Name

Direction

Description

WrAstTxData_o[31:0]

Output

Drives status information to the Descriptor Controller component. Refer to DMA Status Bus table below for more information about this bus.

WrAstTxValid_o

Output

When asserted, indicates that the data is valid.

DMA Descriptor Format

Bits

Name

Description

[31:0]

Source Low Address

Low-order 32 bits of the DMA source address. The address boundary must align to the 32 bits so that the 2 least significant bits are 2'b00. For the Read DMA module, the source address is the PCIe domain address. For the Write DMA module, the source address is the Avalon-MM domain address.

[63:32]

Source High Address

High-order 32 bits of the source address.

[95:64]

Destination Low Address

Low-order 32 bits of the DMA destination address. The address boundary must align to the 32 bits so that the 2 least significant bits have the value of 2'b00. For the Read DMA module, the destination address is the Avalon-MM domain address. For the Write DMA module the destination address is the PCIe domain address.

[127:96]

Destination High Address

High-order 32 bits of the destination address.

[145:128]

DMA Length

Specifies DMA length in dwords. The length must be greater than 0. The maximum length is 1 MB - 4 bytes.

[153:146]

DMA Descriptor ID

Specifies up to 128 descriptors.

[158:154]

Reserved

[159] Immediate Write When set to 1'b1, the Write DMA Engine performs an Immediate Write. The Immediate Write provides a fast mechanism to send a Write TLP upstream. The descriptor stores the 32-bit payload, replacing the Source Low Address field of the descriptor.

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