Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

1.5.2. TX and RX Latency

The TX and RX latency values are based on the following definitions and assumptions:

  • TX latency is the time taken for the data frame to move from the Avalon® streaming interface to the PHY-side interface.
  • RX latency is the time taken for the data frame to move from the PHY-side interface to the Avalon® streaming interface.
  • No backpressure on the Avalon® streaming TX and RX interfaces.
  • All options under Legacy Ethernet 10G MAC interfaces, that allow compatibility with the legacy MAC are disabled.
Table 9.  TX and RX Latency Values for Stratix® 10 DevicesThese latency values are MAC-only latencies and do not include the PHY latencies.
MAC Operating Mode Speed Latency (ns)
TX RX Total
10G 10 Gbps 28.8 41.6 70.4
1G/10G 1 Gbps 156 163.9 319.9
1G/2.5G/10G 1 Gbps 182.7 199.1 381.8
1G/2.5G/10G 2.5 Gbps 106 92.8 198.8
1G/2.5G/10G 10 Gbps 35.2 35.2 70.4
1G/2.5G 1 Gbps 235.2 222.4 457.6
1G/2.5G 2.5 Gbps 140.8 121.7 262.5
10M/100M/1G/10G 10 Mbps 1484.9 20827.7 22312.6
10M/100M/1G/10G 100 Mbps 245.3 2106.1 2351.4
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Gbps 28.8 41.6 70.4
10M/100M/1G/2.5G/5G/10G (USXGMII) 5 Gbps 41.6 67.2 108.8
10M/100M/1G/2.5G/5G/10G (USXGMII) 2.5 Gbps 57.6 118.4 176
10M/100M/1G/2.5G/5G/10G (USXGMII) 1 Gbps 137.6 272.0 409.6
10M/100M/1G/2.5G/5G/10G (USXGMII) 100 Mbps 1162 2576.8 3738.8
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Mbps 12365.5 25624.0 37989.5
10M/100M/1G/2.5G 100 M 1360 1664 3024
10M/100M/1G/2.5G 10 M 12561 17662 30223
10M/100M/1G/2.5G/10G 100 M 1289 1640 2929
10M/100M/1G/2.5G/10G 10 M 14230 17641 31871
Table 10.  TX and RX Latency Values for Arria® 10 and Cyclone® 10 GX DevicesThese latency values are MAC-only latencies and do not include the PHY latencies.
MAC Operating Mode Speed Latency (ns)
TX RX Total
10G 10 Gbps 22.4 38.4 60.8
1G/10G 1 Gbps 148 159 307
1G/2.5G/10G 1 Gbps 182.7 195.9 378.6
1G/2.5G/10G 2.5 Gbps 93.2 89.7 182.9
1G/2.5G/10G 10 Gbps 28.8 32 60.8
1G/2.5G 1 Gbps 238.4 219.2 457.6
1G/2.5G 2.5 Gbps 137.1 112.5 249.6
10M/100M/1G/10G 10 Mbps 1492.9 20822.9 22315.8
10M/100M/1G/10G 100 Mbps 253.3 2104.5 2357.8
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Gbps 22.4 38.4 60.8
10M/100M/1G/2.5G/5G/10G (USXGMII) 5 Gbps 35.2 64 99.2
10M/100M/1G/2.5G/5G/10G (USXGMII) 2.5 Gbps 60.8 115.2 176.0
10M/100M/1G/2.5G/5G/10G (USXGMII) 1 Gbps 137.6 268.9 406.5
10M/100M/1G/2.5G/5G/10G (USXGMII) 100 Mbps 1162.0 2573.6 3735.6
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Mbps 12362.3 25620.8 37983.1
10M/100M/1G/2.5G 100 M 1360 1657.6 3017.6
10M/100M/1G/2.5G 10 M 12561 17656 30217
10M/100M/1G/2.5G/10G 100 M 1289 1637 2926
10M/100M/1G/2.5G/10G 10 M 14227 17638 31865
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