Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

1.5.1. Resource Utilization

The estimated resource utilization for all operating modes are obtained by compiling the Low Latency Ethernet 10G MAC Intel® FPGA IP core with the Quartus® Prime software targeting on Stratix® 10, Arria® 10, and Cyclone® 10 GX devices. These estimates are generated by the fitter, excluding the virtual I/Os.

Table 7.  Resource Utilization for LL Ethernet 10G MAC for Stratix® 10 Devices
MAC Settings ALMs ALUTs Logic Registers Memory Block (M20K)
Operating Mode Enabled Options
10G None. 2,000 2,700 2,900 0
10G Memory-based statistics counters. 2,700 3,600 4,300 4
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

 3,500 4,300 5,900 4
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

Timestamping. Time of day: 96b and 64b.

 7,000 8,100 13,100 19
1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

 3,600 4,500 6,200 4
10M/100M/1G/2.5G/5G/10G (USXGMII)

Supplementary addresses.

Memory-based statistics counters.

 3,000 4,200 5,100 4
10M/100M/1G/ 2.5G/5G/10G (USXGMII)

Supplementary addresses.

Memory-based statistics counters.

Timestamping.

 Time of day: 96b and 64b. 5,800 7,800 10,700 21
Time of day: 96b 5,400 7,100 9,800 20
Time of day format: 64b 4,800 6,300 8,900 17
10M/100M/1G/10G Memory-based statistics counters. 3,400 4,400 5,500 4
10M/100M/1G/10G

Memory-based statistics counters.

Timestamping.

 Time of day: 96b and 64b. 6,800 8,300 12,100 17
Time of day: 96b 6,300 7,700 11,000 17
Time of day format: 64b 5,600 6,700 10,000 13
10M/100M/1G/10G All options enabled except the options to maintain compatibility with the legacy Ethernet 10G MAC. 7,200 8,600 12,400 27
10M/100M/1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

 3,500 4,600 6,100 4
10M/100M/1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

 3,600 4,800 6,800 4
Table 8.  Resource Utilization for LL Ethernet 10G MAC for Arria® 10 and Cyclone® 10 GX Devices
MAC Settings ALMs ALUTs Logic Registers Memory Block (M20K)
Operating Mode Enabled Options
10G None. 1,600 2,400 2,800 0
10G Memory-based statistics counters. 2,400 3,300 4,000 4
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

 2,700 4,100 5,400 5
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

Timestamping. Time of day: 96b and 64b.

 5,500 8,100 13,300 22
1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

 2,900 4,200 5,800 4
10M/100M/1G/2.5G/5G/10G (USXGMII)

Supplementary addresses.

Memory-based statistics counters.

 2,400 3,900 4,700 4
10M/100M/1G/10G Memory-based statistics counters. 2,600 4,000 5,200 4
10M/100M/1G/10G

Timestamping.

Memory-based statistics counters.

 Time of day: 96b and 64b. 5,000 7,600 13,000 21
Time of day: 96b 4,700 7,000 11,800 20
Time of day format: 64b 4,200 6,300 10,700 17
10M/100M/1G/10G All options enabled except the options to maintain compatibility with the legacy Ethernet 10G MAC. 5,400 7,900 13,300 27
10M/100M/1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

 2,900 4,300 5,700 5
10M/100M/1G/2.5G/10G

Supplementary addresses.

Memory-based statistics counters.

 3,000 4,400 6,000 4
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