Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers

Use this table to map the legacy Ethernet 10-Gbps MAC registers to the LL Ethernet 10G MAC registers.

Table 22.  Register Mapping
Register Names (10-Gbps Ethernet MAC)

Offset

(10-Gbps Ethernet MAC)

Offset

(LL Ethernet 10G MAC)
MAC TX Configuration Registers
TX Packet Control 1000 020
TX Transfer Status 1001 Not used.
TX Pad Insertion Control 1040 024
TX CRC Insertion Control 1080 026
TX Packet Underflow Count[31:0] 10C0 03E
TX Packet Underflow Count[35:32] 10C1 03F
TX Preamble Pass-Through Mode Control 1100 028
TX Unidirectional 1120 070
TX Pause Frame Control 1140 040
TX Pause Frame Quanta 1141 042
TX Pause Frame Enable 1142 044
TX PFC0 Pause Quanta 1180 048
TX PFC1 Pause Quanta 1181 049
TX PFC2 Pause Quanta 1182 04A
TX PFC3 Pause Quanta 1183 04B
TX PFC4 Pause Quanta 1184 04C
TX PFC5 Pause Quanta 1185 04D
TX PFC6 Pause Quanta 1186 04E
TX PFC7 Pause Quanta 1187 04F
TX PFC0 Hold-off Quanta 1190 058
TX PFC1 Hold-off Quanta 1191 059
TX PFC2 Hold-off Quanta 1192 05A
TX PFC3 Hold-off Quanta 1193 05B
TX PFC4 Hold-off Quanta 1194 05C
TX PFC5 Hold-off Quanta 1195 05D
TX PFC6 Hold-off Quanta 1196 05E
TX PFC7 Hold-off Quanta 1197 05F
TX PFC Enable 11A0 046
TX Address Insertion Control 1200 02A

TX Address Insertion MAC Address[31:0]

 1201 010

TX Address Insertion MAC MAC Address[47:32]

 1202 011
TX Maximum Frame Length 1801 02C
MAC RX Configuration Registers
RX Transfer Control 0000 0A0
RX Transfer Status 0001 Not used
RX Pad/CRC Control 0040 0A4
RX CRC Check Control 0080 0A6
RX Overflow Truncated Packet Count[31:0] 00C0 0FC
RX Overflow Truncated Packet Count[35:32] 00C1 0FD
RX Overflow Dropped Packet Count[31:0] 00C2 0FE
RX Overflow Dropped Packet Count[35:32] 00C3 0FF
RX Preamble Forward Control 0100 0A8
RX Preamble Pass-Through Mode Control 0140 0AA
RX Frame Filtering Control 0800 0AC
RX Maximum Frame Length 0801 0AE

RX Frame MAC Address[31:0]

 0802 010

RX Frame MAC Address[47:32]

 0803 011
RX Supplementary Address 0[31:0] 0804 0B0
RX Supplementary Address 0[47:32] 0805 0B1
RX Supplementary Address 1[31:0] 0806 0B2
RX Supplementary Address 1[47:32] 0807 0B3
RX Supplementary Address 2[31:0] 0808 0B4
RX Supplementary Address 2[47:32] 0809 0B5
RX Supplementary Address 3[31:0] 080A 0B6
RX Supplementary Address 3[47:32] 080B 0B7
RX PFC Control 0818 0C0
TX Time Stamp Registers
TX Period for 10G 1110 100
TX Fractional Nano-second Adjustment for 10G 1112 102
TX Nano-second Adjustment for 10G 1113 104
TX Period for 10M/100M/1G 1118 108
TX Fractional Nano-second Adjustment for 10M/100M/1G/2.5G 111A 10A
TX Nano-second Adjustment for 10M/100M/1G/2.5G 111B 10C
RX Time Stamp Registers
RX Period for 10G 0110 120
RX Fractional Nano-second Adjustment for 10G 0112 122
RX Nano-second Adjustment for 10G 0113 124
RX Period for 10M/100M/1G 0118 128
RX Fractional Nano-second Adjustment for 10M/100M/1G/2.5G 011A 12A
RX Nano-second Adjustment for 10M/100M/1G/2.5G 011B 12C
All TX Statistics Registers 1Cxx 14x
All RX Statistics Registers 0Cxx 1Cx
Status Registers

ECC Error Status

 Not applicable 240

ECC Error Enable

 Not applicable 241
Level Two Title