Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 12/26/2023
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4.5.8. RX Timing Diagrams

Figure 22. Back-to-back Transmission of Normal Frames with CRC Removal EnabledThe following diagram shows back-to-back reception of normal frames with CRC removal enabled.


Figure 23. Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode EnabledThe following diagram shows back-to-back reception of normal frames with preamble passthrough mode and padding bytes and CRC removal enabled.