Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
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Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5.9. Timestamp Registers

The TX and RX timestamp registers are available when you turn on the Enable time stamping parameter. Otherwise, these registers are reserved.
Table 30.  Timestamp Registers
Word Offset Register Name Description Access HW Reset Value
0x0100 tx_period_10G Specifies the clock period for the timestamp adjustment on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
  • Bits 20 to 31—reserved. Set these bits to 0.
Enabling Use legacy Ethernet 10G MAC XGMII Interface option does not affect the frequency of the datapaths. The default value is 3.2 ns for 312.5 MHz clock. Configure this register before you enable the MAC IP core for operations. 		RW 0x33333
0x0102 tx_fns_adjustment_10G Static timing adjustment in fractional nanoseconds on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x0104 tx_ns_adjustment_10G Static timing adjustment in nanoseconds on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x0108 tx_period_mult_speed Specifies the clock period for timestamp adjustment on the datapaths for 10M/100M/1G/2.5G operations of MII/GMII protocol. This register is not applicable for USXGMII operations. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and GMII/MII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
  • Bits 20 to 31—reserved. Set these bits to 0.

The default value is 8 ns for 125 MHz clock. Configure this register before you enable the MAC IP core for operations.

The IP core automatically sets the clock period for 1G/2.5G configurations. For 1G, the clock period is set to 16 ns for 62.5 MHz clock; for 2.5G, the clock period is 6.4 ns for 156.25 MHz clock.

RW 0x80000
0x0120 rx_period_10G Specifies the clock period for the timestamp adjustment on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
  • Bits 20 to 31—reserved. Set these bits to 0.
Enabling Use legacy Ethernet 10G MAC XGMII Interface option does not affect the frequency of the datapaths. The default value is 3.2 ns for 312.5 MHz clock. Configure this register before you enable the MAC IP core for operations. 		RW 0x33333
0x0122 rx_fns_adjustment_10G Static timing adjustment in fractional nanoseconds on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x0124 rx_ns_adjustment_10G Static timing adjustment in nanoseconds on the datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x0128 rx_period_mult_speed Specifies the clock period for timestamp adjustment on the datapaths for 10M/100M/1G/2.5G operations of MII/GMII protocol. This register is not applicable for USXGMII operations. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and GMII/MII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
  • Bits 20 to 31—reserved. Set these bits to 0.

The default value is 8 ns for 125 MHz clock. Configure this register before you enable the MAC IP core for operations.

The IP core automatically sets the clock period for 1G/2.5G configurations. For 1G, the clock period is set to 16 ns for 62.5 MHz clock; for 2.5G, the clock period is 6.4 ns for 156.25 MHz clock.

RW 0x80000
0x10A tx_fns_adjustment_mult_speed Static timing adjustment in fractional nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x10C tx_ns_adjustment_mult_speed Static timing adjustment in nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x12A rx_fns_adjustment_mult_speed Static timing adjustment in fractional nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x12C rx_ns_adjustment_mult_speed Static timing adjustment in nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved. Set these bits to 0.

Configure this register before you enable the MAC IP core for operations.

For timing adjustment calculations, refer to the related links.

RW 0x0
0x110 tx_asymmetry Specifies the asymmetry value and direction of arithmetic operation.
  • Bits 0 to 16—asymmetry value.
  • Bit 17—direction.
    • Set to 0—add asymmetry value to correction field (CF).
    • Set to 1—minus asymmetry value from CF.
  • Bit 18—enable bit.
 RW 0x0
0x112 tx_p2p

Specifies the direction of arithmetic operation for meanPathDelay.

  • Bit 0— direction.
    • Set to 0—add meanPathDelay value to CF.
    • Set to 1—minus meanPathDelay value from CF.
  • Bits 1 to 30—reserved.
RW 0x0
0x114 tx_cf_err_stat
  • Bits 0—error status bit to indicate that ingress correction field is equal to the absolute maximum, 64’h7FF_FFFF_FFFF_FFFF.
  • Bits 0 to 15—reserved.
  • Bit 16—error status bit to indicate that egress correction field is equal or larger than absolute maximum, 64’h7FFF_FFFF_FFFF_FFFF.
  • Bit 17—error status bit to indicate that residence time is equal or larger than 4 seconds.
  • Bit 18—error status bit to indicate that residence time is a negative value.
  • Bits 19 to 31—reserved.
 RW1C 0x0
0x12E rx_p2p_mpd_ns

meanPathDelay valid and value in ns.

The peer-to-peer mechanism delivers meanPathDelay for each ingress port. This needs to be added to the Sync packet’s correction field before the packet is sent out on egress port. Thus, the egress port might add any of the ingress ports' 'meanPathDelay'. The value to be added at the egress port should correspond to the ingress port on which the Sync packet has arrived.

  • Bit 30—Indicates meanPathDelay is valid.
  • Bits 0 to 29—meanPathDelay value in nanosecond.
  • Bit 31—reserved.
 RW 0x0
0x130 rx_p2p_mpd_fns
  • Bits 0 to 15—meanPathDelay value in fractional nanosecond.
  • Bits 16 to 31—reserved.
 RW 0x0

Section Content
Calculating Timing Adjustments

Related Information
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