Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5.11. Statistics Registers

Statistics counters with prefix tx_ collect statistics on the TX datapath; prefix rx_ collect statistics on the RX datapath. The counters collect statistics for the following frames:

  • Good frame—error-free frames with a valid frame length.
  • Error frame—frames that contain errors or with an invalid frame length.
  • Invalid frame—frames that are not supported by the MAC IP core or its current configuration. For example, if the MAC is configured to receive all unicast frames, unicast frames are considered valid because address filtering is disabled. The MAC drops invalid frames.

Most of the statistics counters are 36 bits wide and occupy two offsets. The user application must first read the lower 32 bits followed by the upper 4 bits.

  • The lower 32 bits of the counter occupy the first offset.
  • The upper 4 bits of the counter occupy bits 3:0 at the second offset.
  • Bits 31:5 at the second offset are reserved.

Consider the following guidelines when using the statistics counters:

  • Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation. Undersized frames are frames with less than 64 bytes.
  • Do not access the statistics counters when the TX and RX datapaths reset are in progress. Doing so can lead to unpredictable results.

Table 35.  TX and RX Statistics Registers
Word Offset Register Name Description Access HW Reset Value
0x0140 tx_stats_clr
  • Bit 0—Set this register to 1 to clear all TX statistics counters. The IP core clears this bit when all counters are cleared.
  • Bits 31:1—reserved.
RWC 0x0
0x01C0 rx_stats_clr
  • Bit 0—Set this register to 1 to clear all RX statistics counters. The IP core clears this bit when all counters are cleared.
  • Bits 31:1—reserved.
RWC 0x0
0x0142 tx_stats_framesOK 36-bit statistics counter that collects the number of frames that are successfully received or transmitted, including control frames. RO 0x0
0x0143
0x01C2 rx_stats_framesOK
0x01C3
0x0144 tx_stats_framesErr 36-bit statistics counter that collects the number of frames received or transmitted with error, including control frames. RO 0x0
0x0145
0x01C4 rx_stats_framesErr
0x01C5
0x01C6 rx_stats_framesCRCErr 36-bit statistics counter that collects the number of RX frames with CRC error. RO 0x0
0x01C7
0x0148 tx_stats_octetsOK 64-bit statistics counter that collects the payload length, including the bytes in control frames. The payload length is the number of data and padding bytes received or transmitted. If the tx_vlan_detection[0] or rx_vlan_detection[0] register bit is set to 1, the VLAN and stacked VLAN tags are counted as part of the TX payload or RX payload respectively. RO 0x0
0x0149
0x01C8 rx_stats_octetsOK
0x01C9
0x014A tx_stats_pauseMACCtrl_Frames 36-bit statistics counter that collects the number of valid pause frames received or transmitted. RO 0x0
0x014B
0x01CA rx_stats_pauseMACCtrl_Frames
0x01CB
0x014C tx_stats_ifErrors 36-bit statistics counter that collects the number of frames received or transmitted that are invalid and with error. RO 0x0
0x014D
0x01CC rx_stats_ifErrors
0x01CD
0x014E tx_stats_unicast_FramesOK 36-bit statistics counter that collects the number of good unicast frames received or transmitted, excluding control frames. RO 0x0
0x014F
0x01CE rx_stats_unicast_FramesOK
0x01CF
0x0150 tx_stats_unicast_FramesErr 36-bit statistics counter that collects the number of unicast frames received or transmitted with error, excluding control frames. RO 0x0
0x0151
0x01D0 rx_stats_unicast_FramesErr
0x01D1
0x0152 tx_stats_multicast_FramesOK 36-bit statistics counter that collects the number of good multicast frames received or transmitted, excluding control frames. RO 0x0
0x0153
0x01D2 rx_stats_multicast_FramesOK
0x01D3
0x0154 tx_stats_multicast_FramesErr 36-bit statistics counter that collects the number of multicast frames received or transmitted with error, excluding control frames. RO 0x0
0x0155
0x01D4 rx_stats_multicast_FramesErr
0x01D5
0x0156 tx_stats_broadcast_FramesOK 36-bit statistics counter that collects the number of good broadcast frames received or transmitted, excluding control frames. RO 0x0
0x0157
0x01D6 rx_stats_broadcast_FramesOK
0x01D7
0x0158 tx_stats_broadcast_FramesErr 36-bit statistics counter that collects the number of broadcast frames received or transmitted with error, excluding control frames. RO 0x0
0x0159
0x01D8 rx_stats_broadcast_FramesErr
0x01D9
0x015A tx_stats_etherStatsOctets 64-bit statistics counter that collects the total number of octets received or transmitted. This count includes good, errored, and invalid frames. RO 0x0
0x015B
0x01DA rx_stats_etherStatsOctets
0x01DB
0x015C tx_stats_etherStatsPkts 36-bit statistics counter that collects the total number of good, errored, and invalid frames received or transmitted. RO 0x0
0x015D
0x01DC rx_stats_etherStatsPkts
0x01DD
0x015E tx_stats_etherStatsUndersizePkts 36-bit statistics counter that collects the number of undersized TX or RX frames. RO 0x0
0x015F
0x01DE rx_stats_etherStatsUndersizePkts
0x01DF
0x0160 tx_stats_etherStatsOversizePkts 36-bit statistics counter that collects the number of TX or RX frames whose length exceeds the maximum frame length specified. RO 0x0
0x0161
0x01E0 rx_stats_etherStatsOversizePkts
0x01E1
0x0162 tx_stats_etherStatsPkts64Octets 36-bit statistics counter that collects the number of 64-byteTX or RX frames, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x0163
0x01E2 rx_stats_etherStatsPkts64Octets
0x01E3
0x0164 tx_stats_etherStatsPkts65to127Octets 36-bit statistics counter that collects the number of TX or RX frames between the length of 65 and 127 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x0165
0x01E4 rx_stats_etherStatsPkts65to127Octets
0x01E5
0x0166 tx_stats_etherStatsPkts128to255Octets 36-bit statistics counter that collects the number of TX or RX frames between the length of 128 and 255 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x0167
0x01E6 rx_stats_etherStatsPkts128to255Octets
0x01E7
0x0168 tx_stats_etherStatsPkts256to511Octets 36-bit statistics counter that collects the number of TX or RX frames between the length of 256 and 511 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x0169
0x01E8 rx_stats_etherStatsPkts256to511Octets
0x01E9
0x016A tx_stats_etherStatsPkts512to1023Octets 36-bit statistics counter that collects the number of TX or RX frames between the length of 512 and 1,023 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x016B
0x01EA rx_stats_etherStatsPkts512to1023Octets
0x01EB
0x016C tx_stats_etherStatPkts1024to1518Octets 36-bit statistics counter that collects the number of TX or RX frames between the length of 1,024 and 1,518 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x016D
0x01EC rx_stats_etherStatPkts1024to1518Octets
0x01ED
0x016E tx_stats_etherStatsPkts1519toXOctets 36-bit statistics counter that collects the number of TX or RX frames equal or more than the length of 1,519 bytes, including the CRC field but excluding the preamble and SFD bytes. This count includes good, errored, and invalid frames. RO 0x0
0x016F
0x01EE rx_stats_etherStatsPkts1519toXOctets
0x01EF
0x01F0 rx_stats_etherStatsFragments 36-bit statistics counter that collects the total number of RX frames with length less than 64 bytes and CRC error. The MAC does not drop these frames. RO 0x0
0x01F1
0x01F2 rx_stats_etherStatsJabbers 36-bit statistics counter that collects the number of oversized RX frames with CRC error. The MAC does not drop these frames. RO 0x0
0x01F3
0x01F4 rx_stats_etherStatsCRCErr 36-bit statistics counter that collects the number of RX frames with CRC error, whose length is between 64 and the maximum frame length specified in the register. The MAC does not drop these frames. RO 0x0
0x01F5
0x0176 tx_stats_unicastMACCtrlFrames 36-bit statistics counter that collects the number of valid TX or RX unicast control frames. RO 0x0
0x0177
0x01F6 rx_stats_unicastMACCtrlFrames
0x01F7
0x0178 tx_stats_multicastMACCtrlFrames 36-bit statistics counter that collects the number of valid TX or RX multicast control frames. RO 0x0
0x0179
0x01F8 rx_stats_multicastMACCtrlFrames
0x01F9
0x017A tx_stats_broadcastMACCtrlFrames 36-bit statistics counter that collects the number of valid TX or RX broadcast control frames. RO 0x0
0x017B
0x01FA rx_stats_broadcastMACCtrlFrames
0x01FB
0x017C tx_stats_PFCMACCtrlFrames 36-bit statistics counter that collects the number of valid TX or RX PFC frames. RO 0x0
0x017D
0x01FC rx_stats_PFCMACCtrlFrames
0x01FD
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