Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 4/09/2024
Document Table of Contents

4.4.1. Padding Bytes Insertion

By default, the MAC TX inserts padding bytes (0x00) into TX frames to meet the following minimum payload length:

  • 46 bytes for basic frames
  • 42 bytes for VLAN tagged frames
  • 38 bytes for stacked VLAN tagged frames

Ensure that CRC-32 insertion is enabled when padding bytes insertion is enabled.

You can disable padding bytes insertion by setting the tx_pad_control register to 0. When disabled, the MAC IP core forwards the frames to the PHY-side interface without padding. Ensure that the minimum payload length is met; otherwise the current frame may get corrupted. You can check for undersized frames by referring to the statistics collected.