Visible to Intel only — GUID: bhc1395127776803
Ixiasoft
Visible to Intel only — GUID: bhc1395127776803
Ixiasoft
5.8. RX Configuration and Status Registers
Word Offset | Register Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x00A0 | rx_transfer_control |
A change of value in this register takes effect at a packet boundary. Any transfer in progress is not affected. |
RW | 0x0 |
0x00A2 | rx_transfer_status | The MAC sets the following bits to indicate the status of the RX datapath.
|
RO | 0x0 |
0x00A4 | rx_padcrc_control |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x1 |
0x00A6 | rx_crccheck_control | CRC checking on receive.
Configure this register before you enable the MAC IP core for operations. |
RW | 0x2 |
0x00A8 | rx_custom_preamble_forward 10 |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x0 |
0x00AA | rx_preamble_control 10 |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x0 |
0x00AC | rx_frame_control | Configure this register before you enable the MAC IP core for operations. |
RW | 0x3 |
Bit 0—EN_ALLUCAST 0: Filters RX unicast frames using the primary MAC address. The MAC IP core drops unicast frames with a destination address other than the primary MAC address. 1: Accepts all RX unicast frames. Setting this bit and the EN_ALLMCAST to 1 puts the MAC IP core in the promiscuous mode. |
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Bit 1—EN_ALLMCAST 0: Drops all RX multicast frames. 1: Accepts all RX multicast frames. Setting this bit and the EN_ALLUCAST bit to 1 is equivalent to setting the MAC IP core to the promiscuous mode. |
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Bit 2—reserved. | ||||
Bit 3—FWD_CONTROL. When you turn on the Priority-based Flow Control parameter, this bit affects all control frames except the IEEE 802.3 pause frames and priority-based control frames. When the Priority-based Flow Control parameter is not enabled, this bit affects all control frames except the IEEE 802.3 pause frames. 0: Drops the control frames. 1: Forwards the control frames to the client. |
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Bit 4—FWD_PAUSE 0: Drops pause frames. 1: Forwards pause frames to the client. |
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Bit 5—IGNORE_PAUSE 0: Processes pause frames. 1: Ignores pause frames. |
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Bits 15:6—reserved. | ||||
Bit 16—EN_SUPP0 0: Disables the use of supplementary address 0. 1: Enables the use of supplementary address 0. |
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Bit 17—EN_SUPP1 0: Disables the use of supplementary address 1. 1: Enables the use of supplementary address 1. |
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Bit 18—EN_SUPP2 0: Disables the use of supplementary address 2. 1: Enables the use of supplementary address 2. |
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Bit 19—EN_SUPP3 0: Disables the use of supplementary address 3. 1: Enables the use of supplementary address 3. |
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Bits 31:20—reserved. | ||||
0x00AE | rx_frame_maxlength |
|
RW | 1518 |
0x00AF | rx_vlan_detection |
|
RW | 0x0 |
0x00B0 | rx_frame_spaddr0_0 | You can specify up to four 6-byte supplementary addresses:
|
RW | 0x0 |
0x00B1 | rx_frame_spaddr0_1 | |||
0x00B2 | rx_frame_spaddr1_0 | |||
0x00B3 | rx_frame_spaddr1_1 | |||
0x00B4 | rx_frame_spaddr2_0 | |||
0x00B5 | rx_frame_spaddr2_1 | |||
0x00B6 | rx_frame_spaddr3_0 | |||
0x00B7 | rx_frame_spaddr3_1 | |||
0x00C0 | rx_pfc_control 11 |
|
RW | 0x1 |
0x00FC | rx_pktovrflow_error | 36-bit error counter that collects the number of RX frames that are truncated when a FIFO buffer overflow persists:
To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read. |
RO | 0x0 |
0x00FD | ||||
0x00FE | rx_pktovrflow_etherStatsDropEvents | 36-bit error counter that collects the number of RX frames that are dropped when FIFO buffer overflow persists:
To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read. |
RO | 0x0 |
0x00FF |