Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021

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4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through

The IOPLL is included in the eSRAM Intel® FPGA IP to drive its clock domains for operation. The testbench should wait for the IOPLL to be locked before starting any simulation to ensure the clock entering the eSRAM is always stable. During the waiting period for the IOPLL to lock, the eSRAM will not function properly due to unstable clock frequency. In hardware, the testbench does not need to check the IOPLL lock signal because the IOPLL lock signal is asserted at the configuration stage, which is handled by firmware. The wait for the IOPLL lock is only needed to perform in software simulation.

You can check the LOCK signal from the output port iopll_lock2core in the eSRAM Intel® FPGA IP design. Simulation can only start after the iopll_lock2core signal goes from LOW to HIGH.

Note: Before starting the simulation, you must provide sufficient delay (for example, 10 us) for the clock to be stable enough after the IOPLL of the eSRAM is locked (iopll_lock2core signal goes from LOW to HIGH).