Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021
Public

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4.4.8.1. Clock Domains

The logic of the FIFO2 Intel® FPGA IP core is separated into 2 clock domains internally:
  • w_clk
  • r_clk

For example, in the default IP setting for a DCFIFO, the 2 clock domains are assumed to be asynchronous with proper clock-crossing structure in place.

You can configure the FIFO2 IP core to operate as a SCFIFO by setting the SCFIFO_MODE parameter to 1. In this mode:
  • All revelant clock crossing structure logic are not synthesized.
  • Both w_clk and r_clk signals are tied together to the same source and timed synchronously.