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1. Intel® Stratix® 10 Embedded Memory Overview 2. Intel® Stratix® 10 Embedded Memory Architecture and Features 3. Intel® Stratix® 10 Embedded Memory Design Considerations 4. Intel® Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Intel® Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Intel® Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Intel® Stratix® 10 Supported Embedded Memory IPs 2.11. Intel® Stratix® 10 Embedded Memory Clocking Modes 2.12. Intel® Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
|How wide should the "shiftin" input and the "shiftout" output buses be?||Specify the width of the data input and output buses. This value is represented by the term w in the Shift Register Memory Configuration.|
|How many taps would you like?||Specify the number of taps. This value is represented by the term n in the Shift Register Memory Configuration.|
|Create groups for each tap output||Turn on this option to create separate groups for output data tapped from the register chain. 47|
|How wide should the distance between taps be?||Specify the distance between taps. This value is represented by the term m in the Shift Register Memory Configuration. 48|
|Create a clock enable port||Turn on this option to create an enable signal for register ports. The register ports are always enabled if this option is not turned on. 49|
|Create an asynchronous clear port||Turn on this option to create an asynchronous clear signal. When asserted, the outputs of the shift register are immediately cleared.|
|Create a synchronous clear port||Turn on this option to create a synchronous clear signal. When asserted, the outputs of the shift register are cleared at the next positive clock edge.|
|What should the RAM block type be?||Choose the type of memory block that supports the feature, memory configuration, and capacity for your application. 50|
- The widths of the shiftin input bus and shiftout output bus are identical, and they are not registered. However, the output data can be considered synchronous with the clock because the internal read address to the memory block is synchronous to the clock.
- The width of the output taps is the multiplication of w (width of input data) and n (number of taps). Also, the word from the MSB of the output taps is equivalent to the shiftout output bus.
47 The combination of these groups represent the taps[wn-1:0] bus.
48 The distance between taps, m, must be at least 3.
49 The registered port is referred to as the internal register at the memory address ports. The shiftin and shiftout ports are not registered.
50 For information about the chosen memory block type, refer to the TriMatrix Embedded Memory Block chapter of your target device handbook. You can also choose AUTO if you are not particular about the RAM block type used. With the AUTO option, the memory block type is determined by the Intel® Quartus® Prime software synthesizer or Fitter at compile time. To determine the type of memory block used, check the Intel® Quartus® Prime Fitter Report.
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