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4.4. FIFO2 Intel® FPGA IP
The FIFO functions in the FIFO2 Intel® FPGA IP core are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains.
|Feature||Intel® FPGA IP Cores|
|Read latency||0 to 1 clock cycle after the rdreq signal is asserted.||3 to 4 clock cycles after the rdreq is asserted.|
|Read valid when||r_empty signal is low.||r_valid signal is high.|
|Show-ahead mode||Supported||Not supported|
|Depth (D) and width (W) configuration||Per user requirement||Multiple of hard memory block only (32W x 512D for M20K, 20W x 32D for MLAB)|
|Output data initial state||0||Unknown|
|Flushing||Not required||A minimum of 32 slow clock cycle flushings is required.|
Before any read-out operations, the applications data is first written (partially or entirely) into the FIFO2 Intel® FPGA IP core. The data read operations can be in long continuous bursts or a single clock read. While there is no specific write or read limitation, the bandwidth utilization will be less efficient for short writes and/or reads due to incurred latencies.
The read interface of the FIFO2 Intel® FPGA IP core is suitable for applications that does not perform back-pressure or for applications with a "cascaded" buffer further downstream.
- At MAC RX user interface, which typically cannot be back-pressured, which is equivalent to always read.
- Along MAX TX internal data path to harden Native PHY FIFO. The FIFO read operations may then be derived from the Native PHY FIFO partial full status.
User application can connect to the read interface of the FIFO2 Intel® FPGA IP core directly to a small SCFIFO (or similar storage buffers) externally to change the read-to-data latency to be zero but at the expense of Fmax and resources.
In practice, all clocks run at several hundred MHz. This is because the FIFO2 Intel® FPGA IP core is highly pipelined to run at very high Fmax, and is not be suitable for slow clocks due to the long latency.
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