126.96.36.199. FIFO2 Parameter Settings
|DATAWIDTH|| FIFO Write and Read Data Width.
The user width granularity is as below, depending on the RAM block type:
This allows up to 4096 bit width which should be more than enough for different applications.
All unused bits (for example, bits that do not carry any information) should be tied-off. For instance, if the user data width were 20-bit and M20K RAM block is used, there would be 12 unused bits to be tied-off.
The default value for n is 1.
|SCFIFO_MODE|| SCFIFO Mode.
Specify whether the FIFO should operate in SCFIFO mode, in which the clock crossing logic structure between Write and Read clock domains shall be removed.
|RAM_BLK_TYPE|| RAM Block Type.
Specify the embedded RAM blocks to be used as the main FIFO storage.
|USE_ACLR_PORT|| Use Asynchronous Clear Port.
Specify whether the asynchronous reset ports (for example, w_aclr and r_aclr) of the IP should have effect.
|WRPTR_GRY_SYNC_CHAIN_LEN|| Write Gray-Code Pointer Synchronizer Chain Length.
Specify the number of flop stages used to synchronize Write Gray-Code Pointer to the r_clk domain.
|RDPTR_GRY_SYNC_CHAIN_LEN|| Read Gray-Code Pointer Synchronizer Chain Length.
Specify the number of flop stages used to synchronize Read Gray-Code Pointer to the w_clk domain.
|RAM_WRPTR_DUPLICATE|| RAM Write Address Duplication.
Specify whether RAM Write Address and associated logic (where appropriate) should be duplicated per RAM block.
|RAM_RDPTR_DUPLICATE|| RAM Read Address Duplication.
Specify whether RAM Read Address (and associated logic where appropriate should be duplicated per RAM block. U