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2.10. Intel® Stratix® 10 Supported Embedded Memory IPs
|IP||Supported Memory Mode||M20K Support||MLAB Support||eSRAM Support||Description|
|RAM: 1-PORT Intel® FPGA IP||Single-port RAM||Yes||Yes||No||You can perform only one read or one write operation at a time.
Use the read enable port to control the RAM output ports behavior during a write operation:
|RAM: 2-PORT Intel® FPGA IP||Simple dual-port RAM||Yes||Yes||No||You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.|
|RAM: 2-PORT Intel® FPGA IP||True dual-port RAM||Yes||No||No||You can perform any combination of two port operations: two reads, two writes, or one read and one write at single clocking mode.|
|RAM: 4-PORT Intel® FPGA IP||Simple quad-port RAM||Yes||No||No||You can simultaneously perform two read and two write operations to different locations where the write addresses are specified at address_a and address_b signal/port, and the read addresses are specified at address2_a and address2_b signal/port.|
|ROM: 1-PORT Intel® FPGA IP||Single-port ROM||Yes||Yes||No||
Only one address port is available for read operation.
You can use the memory blocks as ROM.
|ROM: 2 PORT Intel® FPGA IP||Dual-port ROM||Yes||No||No||
The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.
You can use the memory blocks as a ROM.
|Shift Register (RAM-based) Intel® FPGA IP||—||Yes||Yes||No||
Use the memory blocks as a shift register block to save logic cells and routing resources.
This mode is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.
The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers.
|FIFO Intel® FPGA IP||—||Yes||Yes||No||
You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO functions to implement single- and dual-clock asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.
|FIFO2 Intel® FPGA IP|
|eSRAM Intel® FPGA IP||—||No||No||Yes||
Use eSRAM memory (large memory) to perform a single read and write method. The eSRAM memory has 8 channels . Each channel has dedicated write address and read address, along with write enable and read enable control signal to dynamically control the read and write operation.
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