Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.8. Including the Reset Release Intel® FPGA IP in Your Design

When using the eSRAM Intel® FPGA IP, Intel® requires that you either use the Reset Release Intel® FPGA IP or the INIT_DONE signal route back through a pin to hold this IP in reset until configuration is complete.

To hold the eSRAM Intel® FPGA IP in reset, connect the c<channel_number>_sd_n_0 signal for this IP.